1. Field of the Invention
This invention relates to random access memory apparatus.
2. Description of the Prior Art
Requirements are arising for random access memory apparatus capable of operating at very high writing and reading speeds. For example, a high definition video system has been proposed using 1125 lines per frame and 2048 samples per line, that is, 1125.times.2048 pixels per frame, and 60 fields per second. The system sample rate is therefore nearly 70 MHz, which means that a period of only about 14 nanoseconds is available for processing or storage of the data of each pixel.
Currently it is difficult to provide field or frame stores capable of operating at such high speed, due to problems of power dissipation, and also the small amount of storage per chip and the high cost of memory devices capable of operating at such high speeds. In a video processor, two video field stores are usually employed to form a frame store, such that as one field is being written into the first field store, the previous field is being read from the second field store. During the next field the video data is read from the first field store and the new video field is written into the second field store, the new field overwriting the `used` data contained in the second field store. This process is repeated for each field of video so as to produce a continuous data stream at the output.
A well-known technique which is usable to permit operation at higher speeds is demultiplexing, and a simple example of this is shown in FIG. 1 of the accompanying drawings. In this example, the incoming data is demultiplexed four ways, that is, into four channels, so a memory apparatus 1 comprises four identical random access memories (RAMs) 2, 3, 4 and 5. The pixel data are written sequentially, so successive incoming pixel data are supplied by way of a demultiplexing circuit 6 to the RAM 2, to the RAM 3, to the RAM 4, to the RAM 5, to the RAM 2, and so on cyclically. This means tht each of the RAMs 2 to 5 is only accessed once every four sample periods. Likewise, on reading, the pixel data are read sequentially, so successive pixel data are read from the RAM 2, the RAM 3, the RAM4, the RAM 5, the RAM 2, and so on cyclically, and are combined by a multiplexing circuit 7 for supply to a data output.
While this technique increases by a factor of four the intervals between successive times when a given one of the RAMs 2 to 5 is accessed, or more generally increases it by a factor of N where the data are demultiplexed N ways, there can be a problem resulting from the fact that this technique effectively associates specific portions of a television image with particular channels.
This will now be explained with reference to FIG. 2 of the accompanying drawings. This figure shows diagrammatically two successive horizontal lines L and L+1 of a field, and sequences of vertically-aligned pixels along each of the horizontal lines these pixels being numbered P1 to P10 in each horizontal line. On demultiplexing into four channels A, B, C and D for storage, it being assumed that the number of pixels in each horizontal line is divisible by four, the pixel data will be stored in the random access memories in the respective channels A, B, C and D as indicated. So long as both the writing and reading are sequential along the horizontal lines there is no problem; but consider a case where nonsequential reading is required. For example, in a digital video special effects unit it may be required to rotate the image by 90.degree.. To do this it is necessary sequentially to read out, for example, the data of pixels P1,P1, . . . from successive horizontal lines. But all the pixel P1 data are stored in the random access memory in channel A, so this random access memory has to be accesses at the system sample rate, which is unacceptable. Even where the number of pixels in a horizontal line is not exactly divisible by the number of channels, a predetermined storage pattern of some form will nevertheless exist, and will result in problems in at least some cases of non-sequential reading.
More generally, problems will result with the above known demultiplexing technique in the following three cases:
1. sequential write/non-sequential read PA1 2. non-sequential write/sequential read PA1 3. non-sequential write/non-sequential read. PA1 N memories in each of N channels; PA1 a write enable demultiplexer for selectively supplying write enable signals to said memories; PA1 a write address generator for writing incoming data into all of said memories in any given one of said channels under control of said write enable signals; PA1 a read enable demultiplexer for selecting one of said channels; PA1 a read address generator for reading stored data from any one of said memories in the selected channel and, on reading from a said memory, setting a busy flag for that said memory; PA1 means to clear said busy flag N data periods later; and PA1 means to control said read address generator to step reading onto a different said memory in the same said selected channel, when the said memory to be read has a set busy flag. PA1 N memories in each of N channels; PA1 a write enable demultiplexer for selectively supplying write enable signals to said memories; PA1 a write address generator for writing incoming data allocated by said demultiplexer to any given one of said channels, into one of said memories in said given channel and, on writing into a said memory, setting a busy flag for that said memory, and when said one of said memories has a set busy flag, stepping on to another said memory in said given channel until a said memory without a set busy flag is found; PA1 means to clear said busy flag N data periods later; PA1 respective additional memory means associated with each said memory, for storing a valid data flag for each location in said memory in which data has been written; PA1 means to clear said valid data flag when said data is cleared from the associated location; PA1 a read enable demultiplexer for selecting a particular memory in a channel in dependence on said valid data flags; and PA1 a read address generator for reading stored data from any of said memories and, on reading from a given location in a given said channel, deriving the data from said location in that one of said memories in said channel which has a valid data flag associated with said location.